During the operation of an asynchronous circuit system, especially an Asynchronous SRAM (“ASRAM”), a change on the address line indicates the beginning of a new write or read cycle. Although the ASRAM does not have an external clock, a signal similar to the clock is required to trigger some internal circuits to get ready for the write and read operation, such as pre-charging a bit-line or generating a pulse word-line, etc. An Address Transition Detecting (“ATD”) circuit is used to detect the change on the address line, and to generate a pulse signal for the internal circuits, and the pulse width is an important parameter for the pulse signal. The result of an over-wide pulse is that, the pre-charging of the bit-line still haven't finished when the address decoding has already finished and the word-line is ready for connection, which leads to the delay of the write or read operation. A too narrow pulse will result in insufficient pre-charging of the bit-line, which leads to the delay of the write cycle. Specially, the narrow pulse may lead to failure of the read operation in case of a pulse word-line.
FIGS. 1A and 1B show two known ATD circuits, both of which can detect the rising edge and the falling edge on the address line simultaneously.
As shown in FIG. 1A, the first known ATD circuit comprises a delay circuit 11, three NAND gates 12, 13 and 14, and an inverter 15. An input signal coupled to the input node of the delay circuit 11 is an address signal A1, and the output signals of the delay circuit 11 are signal A1D and signal A1BD. The signal A1D is a delay signal of the address signal A1, which has a delay at the rising edge and falling edge of the address signal A1. The signal A1BD is the inverting signal of the signal A1D. Two input nodes of the first NAND gate 12 are coupled to the address signal A1 and the signal A1 BD, respectively, and an output node of the first NAND gate 12 outputs a pulse signal ATD1BR at the rising edge of the address signal A1. The address signal A1 is coupled to the inverter 15, and two input nodes of the second NAND gate 13 are coupled to the signal A1D and the signal A1B at an output node of the inverter 15, wherein the signal A1B is the inverting signal of the address signal A1. The output node of the second NAND gate 13 outputs a pulse signal ATD1BF at the falling edge of the address signal A1. Two input nodes of the third NAND gate 14 are coupled to the pulse signal ATD1BR and the pulse signal ATD1BF, respectively, and an output node of the third NAND gate 14 outputs a pulse signal ATD1, which has pulses at the rising edge and the falling edge of the address signal A1.
As shown in FIG. 1B, the second known circuit comprises a delay circuit 21, two CMOS transfer gates 22 and 23, and two inverters 24 and 25. An input signal coupled to an input node of the delay circuit 21 is an address signal A2, and output signals of the delay circuit 21 include signal A2D and signal A2BD. The signal A2D is a delay signal of the address signal A2, which has a delay at the rising edge and falling edge of the address signal A2. The signal A2BD is the inverting signal of the signal A2D. The address signal A2 is coupled to the first inverter 25, and an output node of the first inverter 25 outputs signal A2B, which is the inverting signal of the address signal A2. An input node of the first CMOS transfer gate 22 is coupled to the address signal A2, and an input node of the second CMOS transfer gate 23 is coupled to the signal A2B. The signal A2D is coupled to the gate of an NMOS transistor of the first CMOS transfer gate 22, and the signal A2BD is coupled to the gate of a PMOS transistor of the first CMOS transfer gate 22 and the gate of an NMOS transistor of the second CMOS transfer gate 23. Output nodes of the first CMOS transfer gate 22 and the second CMOS transfer gate 23 output a pulse signal ATD2B, which is coupled to the second inverter 24. An output node of the second inverter 24 outputs a pulse signal ATD2, which has pulses at the rising edge and the falling edge of the address signal A2.
The delay circuits 11 in the first known ATD circuit and the delay circuit 21 in the second known ATD circuit can be implemented by various circuits. FIG. 2A shows an example of a known delay circuit, which comprises six inverters 31, four resistors 32 and four capacitors 33. Four delay modules, each of which comprises one resistor 32 and one capacitor 33, are serially coupled between the first five inverters 31 respectively. An input node of the first inverter 31 is coupled to an input signal IN, an output node of the fifth inverter 31 outputs an output signal OUT0, and an output node of the sixth inverter 31 outputs an output signal OUT1. The first and the third capacitor 33 are coupled to a negative power supply VSS or coupled to ground, and the second and the fourth capacitors 33 are coupled to a positive power supply VCC. FIG. 2B shows the waveforms of the input signal and output signals of the known delay circuit. As shown in FIG. 2B, both of the output signals OUT0 and OUT1 have corresponding delays at the rising edge and the falling edge of the input signal IN, wherein the delay time at the rising edge is DLY-R and the delay time at the falling edge is DLY-F. The delay time DLY-R is close to the delay time DLY-F such that a pulse width of the ATD signal, when the rising edge of the address signal A2 is detected, is equal to a pulse width of the ATD signal when the falling edge of the address signal A2 is detected.
FIGS. 3A and 3B show the waveforms of signals of the first and the second known ATD circuits under normal conditions, respectively. During normal operation, an interval PW_ADD between two neighboring address should be one cycle of a write or read operation (tCYC). That is to say, the interval PW_ADD is equal to tCYC, which is bigger than the width of the ATD signal, i.e. DLY_R or DLY_F. The ATD signal in FIG. 3A is the pulse signal ATD1, which has a width of DLY_R at the rising edge of the address signal A1, and a width of DLY_F at the falling edge of the address signal A1. The ATD signal in FIG. 3B is the pulse signal ATD2, which has a width of DLY_R at the rising edge of the address signal A2, and a width of DLY_F at the falling edge of the address signal A2.
If there are some burrs on the address line due to noises, the interval PW_ADD between two neighboring addresses on the address line will be smaller. The width of the burrs is generally small, and therefore the pulse width of the generated ATD signal directly depends on the width of the burrs and is irrelevant to the width DLY_R or DLY_F, as long as the width of the burrs makes the interval PW_ADD smaller than the width DLY_R or DLY_F. FIGS. 3C and 3D show the waveforms of signals of the first and the second known ATD circuits respectively under the condition that burrs exist. As shown in FIGS. 3C and 3D, the widths of the pulse signal ATD1 at the rising edge and falling edge of the address signal A1 are equal to the width of the burrs, namely equal to the width of PW_ADD, which is smaller than the width of the PW_ADD under normal conditions. The widths of the pulse signal ATD2 at the rising edge and the falling edge of the address signal AD2 are equal to the width of the burrs, namely equal to the width of PW_ADD, which is smaller than the width under normal conditions. As described above, a very narrow width of the ATD signal is dangerous, which may result in failure of the read or write operation.